Signals to be preserved for a long time in the form of capacitive charges are subject to decay because of leakage losses. Various systems have already been designed to compensate for such leakage losses, lately with the aid of so-called binary or field-effect capacitors whose capacitance varies between two distinct values upon the application and removal of a certain biasing voltage. Reference in this connection may be made, for example, to the article "BINARE KAPAZITATEN IN MOS-SCHALTUNGEN" by L. Talamonti -- "ELEKTRONIK" 1973 Vol. 5.
In such a system, described as prior art in U.S. Pat. No. 3,943,496, a storage capacitor is temporarily connectable to an external signaling circuit for selective charging and discharging to establish either of the two aforementioned logical values "1" and "0". The storage capacitor is connected through a first field-effect transistor of the insulated-gate type (IGFET) across a supply of direct current and through a second IGFET in series with a binary capacitor (BICAP) across a source of unipolar clock pulses; one of the channel electrodes (source or drain) of each IGFET forms with the storage capacitor a first node or junction communicating, in the conductive state by the second IGFET, with a second node or junction formed by the other channel electrode of the latter IGFET with the control gate of the BICAP. The gate of the first IGFET is tied to this second junction, thus receiving the clock pulses by way of the BICAP, whereas the gate of the second IGFET is permanently biased by the d-c supply.
In the prior-art system just described, the second IGFET conducts as long as the potential of the first junction is at or close to zero level so as to maintain the second junction at virtually the same level. Under these conditions the capacitance of the BICAP is low and lies effectively in series with that of the storage capacitor whereby the applied clock pulses appear at the second junction in greatly attenuated form. When the storage capacitor is charged to the level "one", differing by less than the threshold voltage of the second IGFET from the supply voltage, the potential of the second junction is similarly increased whereby this IGFET is cut off and isolates the storage capacitor from the BICAP whose own capacitance is raised to its high value by the change in the voltage of the second junction. The next clock pulse, therefore, reaches the gate of the first IGFET with a sufficient amplitude to render that IGFET conductive and therefore to enable a recharging of the storage capacitor from the supply to compensate for leakage losses.
Whenever the potential of the second junction drops sufficiently to reactivate the second IGFET, the potential of the first junction decreases. If the leakage loss between clock pulses is so large that the potential of the storage capacitor is reduced to a level well below the difference between the supply and threshold voltages, the conduction of the second IGFET during the occurrence of the next clock pulse (and therefore the presence of the storage capacitor in series with the BICAP) may prevent the retriggering of the first IGFET to replenish the charge of the storage capacitor -- and thus to refresh the stored signal of logical value "one" -- unless the capacitance of the BICAP is large compared with that of the storage capacitor. To ensure proper operation, therefore, the BICAP must be of substantial relative size. In the case of a multistage memory designed to store the several stage outputs of a binary frequency divider in an electronic wristwatch, for example, the resulting dimensions of an integrated-circuit chip may make the use of such a signal-refresher circuit impractical.